The present invention relates to the stacking of multiple wafers to form three-dimensional (3D) semiconductor die structures and, more particularly, relates to the alignment of stacked multiple wafers prior to bonding of the wafers in order to maximize the number of good 3D semiconductor die structures.
Three-dimensional wafer-to-wafer vertical stack technology seeks to achieve the vertical stacking of many layers of active integrated circuit devices such as processors, programmable devices and memory devices inside a single 3D chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance.
In the current process for 3D integration, at least two wafers are placed on each other and then bonded to create a multi-wafer stack. The final stack is then diced into individual die-sized cuboids.